The current ANSI specification (ANSI T1.101 (1993)) sets forth maximum time interval error (MTIE) rate as the maximum allowed peak-to-peak variation between the phases of an input and a synthesized digital data clock over a prescribed time interval. Due to the strict MTIE synchronization accuracy measurement requirement provided in the above ANSI T1.101 specification, compliance problems may arise with respect to the digital data interface that is used to interface digital data received from a digital data link.
One technique to maintain synchronization in digital data communication systems, known as pulse stuffing, selectively inserts pulses into a digital data frame. As described in an article by V. I. Johannes et al, entitled: "Multiplexing of Asynchronous Digital Signals Using Pulse Stuffing with Added-Bit Signaling," IEEE Transactions on Communication Technology, pp. 562-568, October 1966, and an article by D. L. Duttweiler, entitled: "Waiting Time Jitter," Bell System Technical Journal, January 1972, pp. 165-207, the data clock produced at the output of a pulse-stuffing synchronizer, desynchronizer pair contains low frequency jitter, termed waiting time jitter, that cannot be fully removed using the standard phase locked loop filter on the output clock.
Because the receiver circuitry does not have access to the clock of the digital data symbol stream that it is receiving, the receiver must synthesize that clock from the information provided through either the presence or absence of the stuffed pulses. It is important that the synthesized clock be very consistent and regular if it is to be used to distribute network timing information.
In some applications the problem becomes worse because the stuffing pulses are longer than a single unit interval of the data clock. As a result, information passed to the clock smoothing circuit at the desychronizer is rather coarse. (For a description of one non-limiting example of pulse stuffing, as applied to a high bit rate data service loop (HDSL), attention may be directed to the T1E1.4 HDSL Technical Report.)
Thus, there is currently a need for a clock smoothing circuit arrangement for complying with the maximum time interval error in accordance with the current ANSI T1.101 specification applied to a system incorporating pulse-stuffing synchronization, desynchronization, wherein a master oscillator is not locked to the clock driving the incoming or received digital data stream.